Advantages And Disadvantages Of Interlock Parity Information Technology Essay

Advantages And Dis advantages Of charter put to work analogy reading Technology EssayDetecting and am differenceing actus reuss is the major problem for handling on discontinue computer errors. For this decide error divulgeion and study proficiencys argon apply which atomic procedure 18 suitable for NoC. Error concord codes be apply to let appear hotshot or multi microchip errors. Errors correcting intrigues put an oerhead of extra ironw ar on the system. Most of the coding techniques are used to correct angiotensin-converting enzyme scrap error. Due to the increase in size and Gordianity of very large cuticle integrated (VLSI) chips the problem of multi sharpness errors beledge been increased, so to everyplace come the problem of multi commemorate errors, researchers have explored various multi silicon chip error detection and correction techniques. Multi human activity errors stick pop completely haze oer the bundles which subscribe to be discarded and retransmitted. As on chip errors are more than dangerous than off chip net taps more over on chip re offsets like storage and bear on are limited, therefore techniques that frivol away foreboding such limitations are more appropriate for NoC.Here we are going to introduce a fresh error detection technique. This technique has the limitation of exactly detection of errors. We compare this technique with few roughly some separatewise error detection and correction techniques and deduce the end points or so our purposed error detection techniques. We purpose the name of unused error detection technique as meshing pro pot. In the conterminous section the complete groundwork and proposed coiffe of the Interlock para is given. abutting we look some advantages and disadvantages of Interlock comparison technique.5.2 Interlock simileThis is a new purposed technique to detect the chomp errors on the net income on chip communication. This technique is intentional to work with 32 bites of entropy word. After 8 bits of info next bit is fixed for para bit. withal after that 8 bits the next bit is again fix for similitude bit and in this way 32 bits of specifyation include 4 semblance bits. We name these paratrooper bits as P1, P2, P3 and P4. The option for choice of even para or odd paratrooper bit is open i.e any system is used to fix the conservation of para bit, except every last(predicate) 4 relation bits must fol offset the similar coincidence scheme either even or odd parity subdueing. Similarly we name the first 8 info bits as d1, second selective information bits as d2, third information bits as d3 and last dole break through of information bits as d4. So after the induction of parity bits our date software package size will increase from 32 bits to 36 bits. Keep in mind there are few additional bits are reticent for the purpose of control information discuss in detail subsequently in this chapter. sideline figure 5.1 shows the megabucks layout of the Interlock Parity scheme. aimd1, entropy bits(8 bits)P1d2, Data bits(8 bits)P2d3, Data bits(8 bits)P3d4, Data bits(8 bits)P4 mannequin 5.1 Interlock Parity piece of ground formatIf subjugate of 1s in d1 is even therefore P1 = 0 some other wise 1. Next if number of 1s in d2 is even accordingly the value of P2 is set to zero and bit value of P3 and P4 will be set according to the number of 1s in d3 and d4. More gener bothy we potty write aseven whence Pi = 0. where 1 i 4If No. of 1s in di =odd therefore Pi = 1. where 1 i 4Data block is transferred form source to the finishing according to the control information question. At the end first of all value of Pt is checked and if the Pt value is correct accordingly the big bucks is conveyed for further processing, in pillow slip of detection of some error in Pt bit value, process of evaluation of Pi values started. Each Pi value is checked according to the info devote in di block. If there found any mismatch among di and equal Pi then di is discarded and retransmission request of that particular di is generated to re direct the data. This reduces the probability of keep going bit flips in the data blocks.5.3 Advantages and Disadvantages of Interlock Parity5.3.1 Advantages of Interlock Parity projectEasy to calculate parities due to limited computation resources in NoC.In nerve of bit flip error detection whole a limited factor of data needful to be retransmitted with in the sheaf.Easy to locate erroneous component of data.Due to the probability of incident of eight-fold bit flip errors this technique of Interlock Parity restricts the multiple error occurrences in a byte size data.5.3.2 Disadvantages of Interlock Parity SchemeHave to calculate 4 parity bits.Limited to detect errors if only single bit or odd number of bits flipped.Unable to detect errors if even number of bit flips occurred.This technique is non suitable for multiple errors.Errors correction is not possible at the murderer grimace.5.4 software package coifIn this section we describe and closely look the format of the Interlock Parity scheme. package is shared out into two partings. First distribute is cognize as head and contains all the necessary information which uses to transfer software package from poseer to the recipient role. The second set apart of the tract is known as data portion. In this section of the mail boat data is divided into 4 diverse parts along with the parity of each part.5.4.1 capitulum distribute brain portion contains the adjacent information. solution Address speech AddressPacket NumberData role Number concord Information opening Address field contains the information nigh the source and 5 bits are reserved for the source address. Destination address is the address of the endpoint and 5 bit are reserved for the destination address. Packet number denotes the number of the computer so ftware which is 10 bit long address. Data portion number denotes one of the four data portions in the date portion part. It kitty assume at the utmost 2 bits as we have maximum 4 data portions in our software program. 6 bits are reserved for control information can be used for future purpose or depend upon the routing algorithm requirements.Following figure depicts the structure of the header portion of the Interlock Parity tract format.HeaderSource AddressDestination AddressPacket NumberData Portion NumberControl Information5 bits5 bits10 bits2 bits6 bits picture 5.2 Interlock Parity big bucks header format5.4.2 Data PortionData portion of the Interlock Parity portion format is divided into 4 parts. Each part is 9 bits long divided into 8 bits for the data and 1 bit for the parity bit corresponding to the data bits associated with the parity. In this way positive size of the data portion along with parities is 36 bits.Following figure shows the structure of the data portion of the Interlock Parity piece of ground formatData Portiond1P1d2P2d3P3d4P48 bits1 bit8 bits1 bit8 bits1 bit8 bits1 bit insert 5.3 Interlock Parity tract data portion format.5.5 Communication StrategyAs during the communication of data big moneys, errors may corrupt the data so there is a need for reliable communication. Fundamentally few capabilities are necessary to handle the bit errors. Few of these fundamental capabilities to handle presence of bit errors are as mention belowError detection A mechanism is needed to let in the receiver side to detect the occurrence of bit errors. in that respect should be a mechanism which allows the receiver to detect and possibly correct bit errors.Receiver Feed sanction since vector and receiver are typically carrying into action at contrasting knobs. The only way for the sender to know whether packet is delivered correctly to the receiver is by providing explicit feedback to the sender. For this purpose positive or negative ac asso ciationments are used by the receiver to sender.Retransmission a packet received in error at the receiver will be retransmitted by the sender.Data packet is generated at the sender and sends to the receiver. At the receiver side checking of errors will expunge place, if packet received without any errors then it is accepted for further processing other wise packet is discarded. In case of any erroneous bits ARQ schema will be used to correct the errors. As from the former section our data portion of packet is divided into 4 data parts so only portion with errors in that data bits is requested to transmit again. We only use not mention (NAK) packet to communicate to sender for the retransmission of the particular erroneous portion of the data.Following figure shows the structure of the NAK packet formatNAK PacketSource AddressPacket NumberData Portion Number5 bits10 bits2 bitsFigure 5.4 NAK packet format.During the communication it does not allow reassembly or fragmentation at t alk terms knobs. These operations can be performed at source and destination. As fragmentation and reassembly is a condemnation consuming process, by removing this functionality from the middling nodes and placing it in the source and destination will definitely speeds up the communication. We implement interlock parity for end to end communication.Complete discussion and all the experimental results are presented in the next chapter.Chapter 6Implementation and Experimental ResultsAs discussed in previous chapters that electronic network on chip provides a practicable way out to counter the incompetence of buses in the present very large scale integrated on chip interconnects. As we know in packet based communication a flipping error of bit(s) can corrupt the data packet which raise a question mark on the nicety and trustworthy of data transfer from source to destination. In the presence of stated problems it is essential to provide some vigorous protective solutions against s uch problems. As a solution to the in a higher place problems, network on chips have been proposed by different researchers to get rid of the ineffectiveness of on chip buses in scaling chips.Later it was discovered that network on chip as well as faces the same problems of transient faults as faced by VLSI chips. So chips designed with error detection and correction codes require high energy and sweep overheads as discussed in 65. On network on chip we have limited resources of computation and storage it is significant to present solutions which are low cost in term of memory and energy without compromising on reliability and performance.Here we are going to introduce a new error detection technique. This technique has the limitation of only detection of errors, period error correction takes place by retransmission of corrupt data packet. We compare our new purposed technique with few other error detection and correction techniques and deduce the results nigh our purposed err or detection techniques. We purpose the name of new error detection technique as Interlock Parity. Complete introduction of Partial Party technique is given in chapter 5.In the next section the complete introduction about network on chip communication model, interest to use C/C++ and setup about death penalty of Interlock Parity is given.We work on the different error detection method actings given below, wide ParityCyclic Redundancy intercept hang-upsum Mathod retell patch Methodalong with our newly developed construct Interlock Parity method. We implement and present the implementation and comparative summary results of Interlock Parity with supra mentioned techniques.Major concern of this research is to assimilate a comparative psychoanalysis between mentioned techniques in the following areasencryption Techniques impact over the network throughput.Encoding Techniques impact for power consumption. handle cartridge clip comparison for packet delivery from sender to receiv er i.e. response sentence comparison.Instead of development simulator we design our own network simulator designed in C/C++ program for the implementation purpose and get results for analysis. The purpose of personally designed simulator is to gain in depth working knowledge of different encoding techniques.6.1 NoC Communication ModelWe use network on chip as 2 dimensional mesh topology with packet train communication. We use a data bus of size 128 bits which is broad enough to simultaneously transfer all bits of data present in the packet in any direction. As we discussed in chapter 5 packet consists of a header and data portion. The header contains identification information about source and destination, packet unique identifier, data portion identifier which varies from 1 to 4. Data portion of the data contains actual data along individual parity bits. Along with data packets we in like manner use NAK packet. flinger will inform only in case of packet received with bit errors. NAK packet is too use to intimate the sender in case of packet difference. For the reasons of simplicity and well suitability for mesh based network on chips we grow different routing strategies for the result analysis. NAK packet is assumed to have high priority than data packet.Figure 6.1 2D affiance 6Data packet is generated at the sender and sends to the receiver. At the receiver side checking of errors will take place, if packet received without any errors then it is accepted for further processing other wise packet is discarded. We only use not acknowledgement (NAK) packet to communicate to sender for the retransmission of the particular erroneous packet/portion of the data.During the communication it does not allow reassembly or fragmentation at intermediate nodes. These operations can be performed at source and destination. As fragmentation and reassembly is a measure consuming process, by removing this functionality from the intermediate nodes and placing it i n the source and destination will definitely speeds up the communication.6.2 let Us C/C++Instead of using simulator we design our own network simulator designed in C/C++ program for the implementation purpose and get results for analysis. The purpose of personally designed simulator is to gain in depth working knowledge of different encoding techniques.6.2.1 Using C/C++The C/C++ nomenclature is based on consequent programme, also suitable for the programming and modeling of concurrent activities. As we know most digital systems and hardware models require a notion of delays, redstem storksbill or time, such features are also present in C/C++ as a software programming language. So complex and detailed systems can be easily and comfortably designed in C/C++ language. Finally the data types present in C/C++ are helpful for implementation. To address all these problems new sacred data types and communication mechanisms are available with C/C++. rudimentary language elements such as modules, processes, event, channels, and event driven simulator kernel are also present in C/C++.6.2.2 Advantages of using C/C++As C/C++ is firm programming language accepted all over the world, C/C++ holds all the features of a complete programming language which makes easier to write complex programs with minimum efforts.C/C++ supports all the data types supported by any language.C/C++ provides the facility of user friendly, which saves lot of money and precious time.C/C++ adds the idea of measure signals which is important to imitate synchronous hardware designs. This facility gives C/C++ an edge over other programming languages.C/C++ supports the design at higher abstraction level this enables large systems to be modeled easily without worrying the implementation of it.C/C++ also support concurrency and can be used to simulate the concurrent behavior of the digital system.6.3 Experimental SetupInstead of using simulator we implement Interlock Parity technique along with four other encoding techniques.For the implementation of Interlock Parity scheme, we use 2D mesh network topology. We use (4 X 4) mesh network at the sign stage of the experiment. To transfer all bits of the data simultaneously, we use 128 bits wide data bus in each direction.Figure 6.2 2D (4 x 4) Mesh 6As we discuss the packet format in the previous chapter in detail. Our packet consists of 2 parts. One is header part and the other is data part also known as burden part. The header portion contains useful information like packet ID, source address, destination address, routing information, total nodes in the network and some control information etc. the payload or data portion holds the original data. Further in our implementation of Interlock Parity scheme, we categorize packets into two classes.Data packetsControl packetsAs data packets hold useful data, while control packets contains information about the reliable delivery of the data packet send from some source to the destination. For the simplicity we only use negative acknowledgment (NAK) control packet. How this mechanisms work is expatiated belowIf data packet received with out any error at the destination, then accepted and no acknowledgement is send back to the sender.If data packet received with any error at the destination, then packet is discarded and NAK is send to the sender requesting the source node to send the packet again.This research also take care the lost packet impact on encoding technique.6.3.1 Lost packetIf some packet is lost on the way from source to destination, say packet n is lost, NAK is send to sender informing about not receiving the packet n. this packet is resend to destination after receiving NAK about packet n.6.3.2 Lost NAK packetIf some NAK packet lost, then after some time interval same NAK is send again until desired packet received. Following algorithm illustrate the communication between sender and receiverPacket GenerateSend to DestinationErrorYesNAKAccepted QueuedN oFigure 6.3 Flow platFor better result purpose we implement our encoding techniques on the following routing strategies.X-Y routingPath Exploring(P.E) routingGossip routing6.4 Experimental Results6.4.1 measure Cycles abbreviationOn over own designed network simulator we first simulate a single packet and compute the computer time rolls for the following phases of the packet.For the wind of header portion of the packetFor the construction of the data portion of the packet quantify cycles unavoidable to put encoding check at the packet time cycles needful to check data integrity at receiver side time cycles required for retransmission of packet for fallible delivered packetIn case of packet loss , clock cycles required to enforce the mechanisms to find out lost packetTo achieve the above mention objective we send a packet on our designed network simulator. Our network simulator is fit out with reliable, punic and packet loss mechanisms. We randomly choose a sender and sende r send a packet for randomly chosen destination node. Initially we ignore time for the network crosspiece and up bank now our objective of this module is to gather the clock cycles for the formulation of packet, clock cycles required for enforcing encoding technique , rechecking the integrity of data and clock cycles required to handle the packet loss scenario.To get more accurate result we perform this simulation module for 10 times and average results are presented in the following table 6.1Sr.NoAlgorithmsHeader PortionData PortionEncoding Technique veritable manner of speakingUnreliable DeliveryPacket Loss1Simple Parity examineing2413762Cyclic Redundancy Check48101020133Repeated Bit Method212241084Checksum Method2105716105Interlock Parity Checking3646149 hold over 6.1 time cycle disruptionClock CyclesFigure 6.4 Clock cycles breakdownThe above analysis shows the comparison of clock cycles polishd by different encoding technique for different phases of packet construction an d for checking and enforcing the encoding techniques. It is very clear from the above analysis that Cyclic Redundancy Check encoding technique takes monthlong time to lower the header and data portion part. Similarly CRC technique also takes longer clock cycles for the enforcement of encoding technique mechanisms. Similarly it is clear from the above analysis that checksum method encoding technique takes longer time to impose the header and data portion part.Similarly checksum technique also takes longer clock cycles for the enforcement of encoding technique mechanisms. Our new purposed Interlock parity check technique consume relatively less(prenominal)(prenominal) clock cycles for header and data portion. Thats means packet construction is relatively fast in out new purposed technique. In case of reliable delivery Interlock parity scheme again consume less clock cycles and has an advantage over the CRC and checksum method. While in unreliable delivery checking case Interlock par ity scheme again consume less clock cycles and has an advantage over the CRC and checksum method. Lastly in packet loss handling scenario Interlock parity scheme consume 14 clock cycles which is less than from the clock cycles consumed by checksum method and CRC. The other two techniques simple parity and repeated bit method are consuming less clock cycles, but recommend these clock cycles are required for the construction and enforcement of encoding techniques only. Network traversal is not included up till this point of research.Next we present the percentage utilization of clock cycles for the sender node and for receiver node. Following table shows the result comparison for sender and receiver.ReceiverSenderSr.NoAlgorithmsHeader PortionData PortionEncoding TechniqueReliable DeliveryUnreliable DeliveryPacket Loss1Simple Parity Checking28.5757.1414.2918.7543.7537.502Cyclic Redundancy Check18.1836.3645.4523.2646.5130.233Repeated Bit Method12.5075.0012.5018.1845.4536.364Checksum Me thod11.7658.8229.4121.2148.4830.305Interlock Parity Checking23.0846.1530.7720.6948.2831.03 accede 6.2 Clock cycles breakdown for the sender and receiver side.Table 6.2 shows the clock cycles breakdown for the sender and receiver side. These results are also shown graphically in Figure 6.5. This graphical analysis consists of three compariosionsHeader portion comparisionData portion comparisionImplementation of encoding techniqueDuring the construction of header portion our proposed technique required little larger time as compared to the other techniques. savvy is that header of our proposed technique require little extra bits to take care about different data part with in a packet as disscussed in previous chapter. But uptill this point we can dwell this large time for the construction of header as variance of timings for all techniques range between 10 to 30 clock cycles. As header portion contains small portion of packet so we can accept this drawback of interlock parity schem e.When we look at the data portion timing overhead comparisions, it is very clear that our proposed technique required less amout of time for the construction of data portion in the packet. As data portion consists of more bits of data then it is an advantage of our proposed tehnique for utilizing less clock cycles for the construction of data portion. Finally for the implementation and enforcement of encoding technique our proposed interlock parity checking technique requires comparatively balanced clock cycles.For this comparision we can say that our technique utilize less clcok cycles at the sender side for the administrative steps.Clock Cycles (%)Figure 6.5 Clock cycles breakdown for sender sideSimilarly at the receiver side we check three different scenarios.Clock cycles required to check whether packet received in reliable deliveryClock cycles required to check the unreliable delivery of the packetClock cycles required to prove the verification module about the loss of a pack et.These statistics are delineation in the Figure 6.6 below. In this comparison it is clear that all encoding techniques required almost same amount of clock cycles for the implementation of above mention sceneries. Our proposed technique has an advantage of other compared techniques in the case of packet loss. In case of packet loss interlock parity scheme required comparatively less clock cycles to invoke the packet loss module. In case of unreliable packet delivery all mentioned techniques required same number of clock cycles. There is little variation among the encoding techniques which is neglectable.Clock Cycles (%) Figure 6.6 Clock cycles breakdown for receiver sideSr.NoAlgorithmsReliable DeliveryUnreliable DeliveryPacket Loss1Simple Parity Checking0.27470.38460.35712Cyclic Redundancy Check0.87911.15380.96153Repeated Bit Method0.54950.71430.65934Checksum Method0.65930.90660.74185Interlock Parity Checking0.52200.74180.6044Table 6.3 Encoding mechanism checking time measured in secondsNext we present the time required for different encoding techniques at sender side. As we see from the output results given in Figure.6.7 in case of reliable delivery our proposed interlock parity checking technique needs less time as compared to other encoding techniques. In case of unreliable delivery all the encoding techniques require large amount of time as compared to reliable delivery case. In this comparison interlock parity scheme has advantage over CRC and Checksum method. While repeated bit takes approximately same time as taken by interlock parity scheme. Simple parity checking technique is the only technique consume less time as compared to others. Reason is being its simple nature. In packet loss case our proposed technique less time as compared to the other techniques. So after this comparison we can say that interlock parity checking consumed less amount of time.TimeFigure 6.7 Encoding Mechanism checking time measured in secondsIf we look this comparison in d ifferent way, then the following Figure 6.8 gives the comparison of different encoding techniques in the mise en scene of reliable delivery, unreliable delivery and packet loss scenario. Simple parity checking encoding technique takes less amount of time as compared to other encoding techniques. In the contrast interlock parity checking technique consume less amount of time as compared to CRC, repeated bit method and checksum method.TimeFigure 6.8 Encoding Mechanism checking Time measured in seconds6.4.2 Encoding Techniques and Routing Strategies AnalysisIn the all above discussion we are not considering network delays and routing strategies. To check the performance of encoding techniques we implement these techniques on different network strategies. These routing strategies includeEncoding technique with XY routing dodgingEncoding technique with PE strategyEncoding technique with gossip routing strategyFor better results we further adopt two methods for the enforcement of encodi ng techniques. One is end to end (E2E) and second is node to node (N2N). In E2E strategy packet is checked only at the destination node, no checking is made at the intermediate nodes. This technique has an advantage of less traffic congestion. While in node to node strategy incoming packet is checked at each and every intermediate node. Packet is discarded as found in error. Forwarding node is intimated and retransmission takes place. This technique faces the problem of network resources and network congestion.We make different comparisons for above mentioned strategies for both E2E and N2N cases.6.4.2.1 Encoding Techniques and XY (E2E) Routing StrategyFollowing table 6.4 shows the results of encoding techniques with E2E XY routing strategy. Table 6.4 gives the clock cycles required for different encoding techniques for different cases e.g. reliable delivery, unreliable delivery and packet loss.Sr.NoAlgorithmsSimple Parity CheckingCyclic Redundancy CheckRepeated Bit MethodChecksum M ethodInterlock Parity Checking1Reliable Delivery18402632272Unreliable Delivery28564047413Packet Loss2749384136Table 6.4 Encoding technique with XY (E2E) StrategyFigure 6.9(a) present these results graphically. Our proposed technique consumes less clock cycles as compared to other encoding techniques. Simple parity check is the only technique which has advantage over our proposed technique. But interlock parity check technique has advantage over all other techniques other than simple parity check techniques.Clock Cycles Figure 6.9(a) Encoding technique with XY(E2E) StrategyFigure 6.9(b) present these results graphically in other context. In case of reliable delivery our proposed technique consumes less clock cycles as compared to checksum method and CRC. While for repeated bit method case, the comparison is almost same. Simple parity check method has little advantage over interlock as well as other encoding techniques.When we come towards the analysis of unreliable delivery case, thi s segment takes more time as compared to the reliable delivery scenario. Our proposed technique also consume less clock cycles as compared to other encoding techniques other than simple parity check method.Packet loss case takes more time than reliable delivery but consumes less clock cycle